As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option is an information handling system. An information handling system generally processes, compiles, stores, or communicates information or data for business, personal, or other purposes. Technology and information handling needs and requirements can vary between different applications. Thus information handling systems can also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information can be processed, stored, or communicated. The variations in information handling systems allow information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems can include a variety of hardware and software resources that can be configured to process, store, and communicate information and can include one or more computer systems, graphics interface systems, data storage systems, networking systems, and mobile communication systems. Information handling systems can also implement various virtualized architectures. Data and voice communications among information handling systems may be via networks that are wired, wireless, or some combination.
Information handling systems typically use a basic input/output system (BIOS) to perform fundamental operations, such as performing a power on self test (POST), loading an operating system (OS), and other low level operations. The BIOS uses firmware (FW) instructions executed by a processor, such as a central processing unit (CPU) to perform the operations it provides. As technology advances, updating of BIOS FW can occur frequently. When a BIOS update fails, the information handling system may be rendered non-functional, and the motherboard on which the device storing the BIOS FW is located may have to be dispatched for repair.
Any of several things can go wrong during a BIOS update. As an example, a power outage may occur, preventing the BIOS update from being completed and leaving the BIOS in an improper state. While some attempts to provide a BIOS recovery feature have been made, they have been suffered from some limitations. As an example, they have imposed a significant component cost and occupied a significant amount of circuit board area. Typically, a BIOS recovery feature has required a second System Peripheral Interface (SPI) flash memory device of the same density as the main SPI flash memory device connected to the platform controller hub (PCH) or a single SPI flash memory device with a multiplexer to switch the SPI master, so that the BIOS serves as the SPI master during normal run-time and the baseboard management controller (BMC) serves as SPI master during recovery.
Some attempts to provide a BIOS recovery feature pose a security risk. As an example, having an out of band (OOB) processor (such as, a BMC) take over a BIOS SPI flash memory region can be potentially dangerous, as the memory region ownership arbitration between the BIOS, a management engine (ME), and an innovation engine (IE) with the BMC may result in a secondary system hang. A security risk can also exist if the BMC does not perform a signed update validation on the new BIOS image to be stored.
According to one technique, BIOS recovery has been achieved with dual BIOS images (such as, two BIOS SPI flash memory devices attached to a PCH). However, a need for two memory devices results in higher component costs. Also, security authentication limitations exist with such a technique. Another technique has used a multiplexer that allows a BMC having write capability to write to the BIOS SPI flash memory device attached to the PCH. However, the cost of the multiplexer increases component cost, and the technique does not solve the security authentication limitations. Yet another technique is to have BIOS boot SPI flash memory to be behind an embedded controller (EC) or BMC, which introduces another set of issues, which may include, for example, reliability or dependency on the BMC during a normal boot when the BMC is not yet ready, especially during alternating current (AC) power-up.
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